The present invention relates to a device for computing a floating point number and, more particularly, to a floating point number computing device capable of simplifying a procedure to follow the computation of a floating-point number so as to promote rapid floating-point computation.
The present invention is applicable to a computing device using a floating-point number format whose base is 16. One of the conventional floating-point number formats is taught by John P. Hayes in "COMPUTER ARCHITECTURE AND ORGANIZATION", pp. 197-198. In this type of format, four bits of a mantissa are treated as a single unit. Let the unit consisting of such four bits be referred to as a digit hereinafter. The values on the consecutive digits of the mantissa are each represented by a single digit hexadecimal number. The mantissa consists of a predetermined number of digits. The predetermined number of digits and the predetermined number will be referred to as "valid digits" and "a valid number of digits", respectively.
In the event of computation, protection bits are added to opposite ends of the valid digits to enhance the precision of the result of computation. Let the number of digits inclusive of the protection bits be called "an extended number of digits". During computation, various operations are executed with the precision of the extended number of digits.
After the computation, three different kinds of processing are employed to determine the result of computation by the valid number of digits, as follows.
In the first processing, "postprocessing of a mantissa", (i.e., processing wherein, when the result of computation of a mantissa is negative a complement of the mantissa is computed). The postprocessing of the mantissa is accompanied by the inversion of a sign bit. The inversion of a sign bit will be called "sign processing" hereinafter.
The second processing is "rounding" corresponding to rounding a decimal number to the nearest whole number. Specifically, rounding adds hexadecimal 8H to the protection bit immediately following the valid digits.
The third processing is "normalization" which shifts the result of computation to prevent the value on the most significant valid digit from being zero. At the same time, normalization corrects an exponent field.
A fundamental type of floating-point computing device sequentially executes the computation of a mantissa, postprocessing of the mantissa, first normalization, rounding, and second normalization in this order. Such four sequential steps are repeated every time a computation is effected. Therefore, by omitting some of the steps, it is possible to noticeably increase the processing speed of the program.
For example, an implementation for omitting the first normalization mentioned above is proposed in Japanese Patent Laid-Open Publication No. 33539/1986. This implementation has a first NAND gate circuit for detecting a condition wherein all the four bits constituting the most significant digit of the mantissa are "0", and a second NAND gate circuit for detecting a condition wherein all the four bits constituting the digit just to the right of the most significant digit are "0". A constant to be added by rounding is selected on the basis of the outputs of the first and second NAND gate circuits and the kind of computation to be performed. This constant is shifted beforehand by the number of shifts which the mantissa would otherwise undergo during the first normalization. This eliminates the need for the first normalization.
However, the implementation stated above cannot omit processing other than the first normalization.